Gate Logic

A technique for implementing Boolean functions using logic gates

Logic Gates

• Elementary: NAND, AND, OR, NOT
• Composite: MUX, ADDER

NAND

Function:

def NAND(a, b):
    return (a == 1 and b == 1)? 0 : 1

Truth Table:

x	y	NAND
0	0	1
0	1	1
1	0	1
1	1	0

AND

def AND(a, b):
    return (a == 1 and b == 1)

OR

def OR(a, b):
    return (a == 1 or b == 1)

NOT

def NOT(a):
    return not a

Composite Gates

Interface

• Answer the question of "what"
• Abstraction for the user
• Unique for each functionality

Implementation

• Answer the question of "how"
• For the engineers
• Multiple ways to implement

MUX (Multiplexer)

Also called data selector If seg is 0, out = a, else out = b

$$Z=(A\wedge \mathrm{\neg }{S}_0)\vee (B\wedge S_0)$$

**Diagram**

HDL

/** 
 * Multiplexor:
 * if (sel = 0) out = a, else out = b
 */
CHIP Mux {
    IN a, b, sel;
    OUT out;

    PARTS:
    Not (in=sel, out=Notsel);
    And (a=a, b=Notsel, out=aAndNotsel);
    And (a=sel, b=b, out=bAndsel);
    Or (a=aAndNotsel, b=bAndsel, out=out);
}

DMUX (Demultiplexer)

Demultiplexers take one data input and a number of selection inputs, and they have several outputs.

If the input is always true, demultiplexers can act as binary decoders, selecting the bits of corresponding output.

Expression

$$\begin{array}{rl}A& =(I\wedge \mathrm{\neg }S)\\ B& =(I\wedge S)\end{array}$$

Truth Table

In	Sel	a	b
0	0	0	0
0	1	0	0
1	0	1	0
1	1	0	1

**Diagram**

HDL

/**
 * Demultiplexor:
 * [a, b] = [in, 0] if sel = 0
 *          [0, in] if sel = 1
 */
CHIP DMux {
    IN in, sel;
    OUT a, b;

    PARTS:
    Not (in=sel, out=Notsel);
    And (a=in, b=Notsel, out=a);
    And (a=in, b=sel, out=b);
}